VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate
نویسندگان
چکیده
منابع مشابه
VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate
In this work, we present a FPGA design and implementation of a parallel architecture of a low complexity LDPC decoder for high data rate applications. The selected code is a regular LDPC code (3, 4). VHDL design and synthesis of such architecture uses the decoding by the algorithm of BP (Believe propagation) simplified "Min-Sum". The complexity of the proposed architecture was studied; it is 63...
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ژورنال
عنوان ژورنال: International Journal of Advanced Computer Science and Applications
سال: 2017
ISSN: 2156-5570,2158-107X
DOI: 10.14569/ijacsa.2017.080435